Many integrated digital systems, such as memory circuits, are provided with a plurality of output buffers for processing and/or handling the output of digital data streams. Nevertheless, there usually exists a problem that in the case where data are outputted, a noise issue will always occur due to the internal resistive drop and/or inductive effects in the output paths. Further, during the phase change of the output signals, the switching noise problem is particularly intense. When the voltage level in an output terminal of the output buffers is changed from a logic high level to a logic low level, or from the logic low level to the logic high level, the output buffer will absorbs a relatively large current to change the external load capacitance. This causes a noise spike that will slow down the transmission of the signal inside the memory circuit and may cause errors.
In order to overcome the above-mentioned issues, a well-known proposal is to preset the voltage in the output buffers to an intermediate voltage level before outputting the signal. In such a manner, the current flown the output buffer and the voltage discrimination level will be reduced, and therefore the reading speed will be increased and the switching noise will be decreased.
U.S. Pat. No. 4,992,677 discloses a pre-set circuit presetting the output terminal at a certain intermediate voltage level before outputting the signal. Please refer to FIG. 1, which shows an equivalent circuit of the pre-set circuit according to the prior art. As shown in FIG. 1, the pre-set circuit 10 includes a first MOSFET 11 and a second MOSFET 12 connected in series, a first differential amplifier 15 and a second differential amplifier 16, which are electrically connected to the first and the second MOSFETs 11, 12 and supplied with a first reference voltage 17, and a second reference voltage 18, respectively. The first MOSFET 11 is further electrically connected to a supply voltage 2, and the second MOSFET 12 is further electrically connected to a ground 3 in order to provide the potential controlling the flow direction of the current. With such circuit, when an output terminal 1 between the first and the second MOSFETs 11, 12 has an output voltage, Vo, higher than the second reference voltage 18, the second MOSFET 12 will be activated and a current iL will flow from the output terminal to the ground for lowering the output voltage to a level of the second voltage 18; while the output voltage is lower than the first reference voltage 17, the first MOSFET 11 will be activated and a current iH will flow from the supply voltage to the output terminal for raising the output voltage to a level of the first voltage 17.
According to the descriptions in the U.S. Pat. No. 4,992,677, although the MOSFETs 11, 12 of the pre-set circuit 10 can be constructed by the NMOSFETs, bipolar transistor or constructed by combining an NMOSFET and a PMOSFET, it still exists some drawbacks. For example, no matter what kinds of transistors are used, only one MOSFET will be activated during the operation of the pre-set circuit. As a result, the pre-set circuit 10 according to the prior art inevitably needs two differential amplifiers as the comparators, and needs two reference voltages for controlling the operations of the respective transistor electrically connected to the comparator. Nevertheless, if more components are used in the pre-set circuit, the layout area of the pre-set circuit will be increased, and the layout of the circuitry will be more complicated. Further, the cost for fabricating such pre-set circuit will also be more expensive. Therefore, it is necessary to develop a novel memory circuit with a pre-set circuit for increasing the reading speed and decreasing the switching noise thereof.